Semiconductor manufacturing processes are employed to create integrated circuit (IC) dice, which may be packaged into modular microelectronic assemblies or IC chips for incorporation into electronic systems. This modular approach is driven by the large design and set up costs and the miniscule marginal costs typical of the semiconductor industry, which combine to make the IC products commercially feasible only when a sufficiently large number are manufactured. To maximize their market, the packaged products are equipped with interfaces that enable operation in a variety of contexts.
In particular, this approach militates that the input and output (abbreviated as I/O or IO) contacts be designed for robust operation so as to support signal transfer over suboptimal connections and/or to tolerate electrostatic discharges or other signal transients. Accordingly, IC dice traditionally employ, for each IO contact, a “standard IO cell” including circuitry that protects the delicate on-chip circuitry from a range of external phenomena while providing power for driving output signals onto loaded signal traces and/or for conditioning potentially attenuated and noisy input signals. As the number of IO contacts increases, the area and power requirements for the standard IO cells can dominate the requirements for the on-chip circuitry and in extreme cases may become prohibitive.
Before manufacturing begins, the circuit operation is preferably verified using one or more of the modeling techniques disclosed in the open literature. These modeling techniques include full circuit emulation, though it becomes infeasible for even moderately complex circuits. Static timing analysis (STA) is a popular modeling technique for digital circuits because it is relatively fast, analyzing the circuit in terms of timing constraints and propagation delays to determine transition arrival times for comparison with timing requirements, enabling the calculation of timing margins (“slack”) and the discovery of potential timing violations.
The standard IO cells (in this case, standard digital IO cells) are traditionally treated as an outer boundary for static timing analysis for any of multiple reasons including: the permissible degree of variation for the impedance properties of each external trace; the expected variation in loading of different IO contacts; and the greater potential for contamination by signal crosstalk and noise. When a designer wishes to model the behavior of an IC die in the context of a larger electronic assembly, such considerations may require the use of full circuit emulation for proper modeling, despite the aforementioned infeasibility for even moderately complex circuits. Multi-chip modules (MCM), such as those created using 2.5D technology (i.e., microelectronic assemblies formed by mounting multiple IC dice in a “flip-chip” configuration on an “interposer” substrate that provides inter-die connections and connections to the package contacts) with more than a few dice will generally have a complexity beyond this threshold.